Program-controlled unit with on-chip debug resources able to control watchdog timers

ABSTRACT

A program-controlled unit includes a core for executing the program to be executed by the program-controlled unit, and debug resources for tracking and influencing the operations proceeding within the core. The program-controlled unit is distinguished by the fact that the debug resources are able also to influence other components of the program-controlled unit and/or the cooperation of these components with one another and/or with the core. Such action makes it possible to avoid to the greatest possible extent, in a simple manner, the situation wherein disturbances or errors that do not occur in normal operation of the program-controlled unit occur during the debugging or emulation of the program-controlled unit, and/or wherein errors that occur in normal operation of the program-controlled unit do not occur during the debugging or emulation of the program-controlled unit.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a program-controlled unit, having acore for executing the program to be executed by the program-controlledunit, and having debug resources for tracking and influencing theoperations proceeding within the core.

Program-controlled units, such as microprocessors, microcontrollers,signal processors, etc., exist in innumerable embodiments and do notrequire more detailed explanation.

A problem of such program-controlled units is that it is often notpossible or not readily possible to localize and eliminate errors thatoccur.

For such a reason, there has been a changeover to equippingprogram-controlled units with debug resources that make it possible totrack and influence the operations proceeding within theprogram-controlled unit. These debug resources include, for example, theprior art on-chip debug support modules or OCDS modules.

Such and other debug resources make it possible to monitor theoccurrence of states or events within the program-controlled unit, whichstates or events can be prescribed from outside the program-controlledunit, and, when such a state or such an event has occurred, to carry outactions that can be prescribed from outside the program-controlled unit.

The states or events whose occurrence can be monitored by the debugresources may include, by way of example, but not exclusively:

-   -   the access by the program-controlled unit or specific components        thereof to specific memory addresses or registers; and/or    -   the transfer of specific data within the program-controlled        unit; and/or    -   the position of the instruction pointer.        The actions that the debug resources execute when such a state        or other state or event occurs may include, by way of example,        but likewise not exclusively:    -   reporting of the fact that the condition to be monitored has        occurred, to a device provided outside the program-controlled        unit;    -   the read-out or the alteration of the content of specific memory        elements or registers;    -   the outputting of trace information, i.e., the outputting of        addresses, data, and/or control signals that are used or        transferred within the program-controlled unit, to a device        provided outside the program-controlled unit;    -   the stopping of the program execution;    -   the continuation of the program execution in the so-called        single-step mode; or    -   the execution of routines serving for the debugging or emulation        of the program-controlled unit.

The provision of such debug resources in program-controlled units, thus,affords a whole host of possibilities for localizing and eliminatingerrors occurring in the program-controlled unit.

An existing disadvantage of such debug resources is that it is therebyoften not possible to examine the program-controlled unit in real time.By way of example, if the debug resources cause the core of theprogram-controlled unit:

-   -   to stop the program execution; or    -   to continue the program execution in the single-step mode; or    -   to execute instructions that do not belong to the (application)        program that is actually to be executed, but, rather, are        instructions serving for the debugging or emulation of the        program-controlled unit,        the program-controlled unit often behaves differently than is        the case in normal operation thereof. The consequence of such        behavior is that errors that occur in normal operation of the        program-controlled unit often do not occur during the debugging        or emulation of the program-controlled unit using the debug        resources, and/or that errors that do not occur in normal        operation of the program-controlled unit occasionally occur        during the debugging or emulation of the program-controlled unit        using the debug resources.

This greatly limits the possibilities for use of the debug resources. Inparticular, errors occurring in complex program-controlled units orapplications are often not localized and eliminated by the debugresources, or are only partly localized and eliminated, or are localizedand eliminated only with a very high outlay.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide aprogram-controlled unit that overcomes the hereinafore-mentioneddisadvantages of the heretofore-known devices of this general type andthat localizes and eliminates errors occurring in the program-controlledunit under all circumstances rapidly and simply.

With the foregoing and other objects in view, there is provided, inaccordance with the invention, a program-controlled unit, including acore for executing a program, debug resources connected to the core fortracking and influencing operations proceeding within the core, othercomponents connected to at least one of the debug resources and thecore, and the debug resources influencing at least one of the othercomponents and cooperation of the other components with at least one ofone another and the core.

The program-controlled unit according to the invention is distinguishedby the fact that the debug resources are able also to influence othercomponents of the program-controlled unit than the core itself and/orthe cooperation of these components with one another and/or with thecore.

Such ability makes it possible to avoid problems that occur inconventional program-controlled units if the debug resources put thecore into a state in which the latter behaves differently than in normaloperation. In particular, it is, thus, possible to avoid the problemsthat result from the fact that the components of the program-controlledunit no longer operate and/or cooperate as intended in the case of analtered behavior of the core.

By virtue of the possibility of putting not only the core but also othercomponents of the program-controlled unit into a state in which thesebehave differently than in normal operation, the behavior of the othercomponents can be adapted to the altered behavior of the core. It ispreferably provided that when the debug resources put the core of theprogram-controlled unit into a state in which the latter behavesdifferently than in normal operation, these debug resourcesautomatically simultaneously adapt the other components of theprogram-controlled unit to the altered behavior of the core.

This makes it possible to avoid to the greatest possible extent, in asimple manner, the situation wherein disturbances or errors that do notoccur in normal operation of the program-controlled unit occur duringthe debugging or emulation of the program-controlled unit, and/orwherein errors that occur in normal operation of the program-controlledunit do not occur during the debugging or emulation of theprogram-controlled unit.

In accordance with another feature of the invention, the othercomponents are components having behavior influencing a behavior of thecore.

In accordance with a further feature of the invention, the othercomponents include at least one watchdog timer.

In accordance with an added feature of the invention, the debugresources deactivate the other components, turn off the othercomponents, place the other components into a given state, reset theother components, reconfigure the other components, and/or alter signalsfed to the other components.

In accordance with an additional feature of the invention, theinfluencing of the other components by the debug resources is adeactivation of the other components, a turning off of the othercomponents, a placement of the other components into a given state, areset of the other components, a reconfiguration of the othercomponents, and/or an alteration of signals fed to the other components.

In accordance with yet another feature of the invention, the debugresources prevent the other components from cooperating.

In accordance with yet a further feature of the invention, the debugresources initiate cooperation of components not otherwise cooperating.

In accordance with yet an added feature of the invention, the debugresources at least one of carry out influencing of the other componentsand carry out the cooperation of the other components at least one ofwith one another and with the core automatically when predefined eventsoccur.

In accordance with yet an additional feature of the invention, thepredefined events include an altering of an overall behavior by actionsexecuted by the debug resources.

In accordance with a concomitant feature of the invention, the debugresources executing actions altering a behavior of the core, the debugresources stopping execution of the program, the debug resourcesaltering a speed at which the program is executed, the debug resourcescausing the core to execute the program in a single-step mode, the debugresources causing execution of instructions not part of the program,and/or the debug resources causing execution of instructions of one of adebugging program and an emulation program.

Other features that are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein asembodied-in a program-controlled unit, it is, nevertheless, not intendedto be limited to the details shown because various modifications andstructural changes may be made therein without departing from the spiritof the invention and within the scope and range of equivalents of theclaims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof, will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic illustration and block circuit diagram of aprogram-controlled unit in accordance with a first exemplary embodimentof the invention; and

FIG. 2 is a diagrammatic illustration and block circuit diagram of aprogram-controlled unit in accordance with a second exemplary embodimentof the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The program-controlled unit described below is a microcontroller.However, it is noted that the special features of the microcontrollerthat are described below can also be provided in any otherprogram-controlled units, such as microprocessors, signal processors,etc.

The program-controlled units described below are distinguished by thefact that their debug resources are able to influence not only the corebut also other components of the program-controlled unit and/or thecooperation of these components with one another and/or with the core.

For the sake of completeness, it is noted that the components of theprogram-controlled units considered that are illustrated and describedare only the components that are of particular interest in the presentcase.

Referring now to the figures of the drawings in detail and first,particularly to FIG. 1 thereof, there is shown a program-controlled unitcontaining a core C, memory devices S1 to Sn connected to the core Cthrough a first bus BUS1, periphery units P1 to Pn connected to the coreC through a second bus BUS2, a watchdog timer WD, and an OCDS moduleOCDS.

The core C reads data representing instructions and operands from thememory devices S1 to Sn or from an external memory device that isprovided outside the microcontroller and is not shown in FIG. 1, andexecutes the data.

The memory devices S1 to Sn may be formed by a ROM, a flash memory, aRAM, or by any other memory devices.

The peripheral units P1 to Pn are, for example, an A/D converter, atimer, a coding device, a DMA controller, a CAN controller, a USBcontroller, or other devices that can be integrated in microcontrollers.

The watchdog timer WD is a counter that:

-   -   automatically counts upward or downward in a specific timing;    -   is reset when predetermined events occur; and    -   executes or initiates a specific action when a specific count is        reached, the action including, for example, in the watchdog        timer WD resetting, or putting into a specific other state,        either the program-controlled unit in its entirety or,        alternatively, at least the core C and/or one or more other        components of the program-controlled unit.

The construction, the function and the method of operation of watchdogtimers exist in the prior art so that the description of further detailscan be dispensed with.

The OCDS module OCDS is an OCDS module of the type mentioned in theintroduction, but has a number of special features by comparisontherewith. For the sake of completeness, it is noted that the OCDSmodule can be connected to a device provided outside theprogram-controlled device through one or more input and/or outputterminals of the program-controlled unit, for example, through a JTAG ora NEXUS interface. The external device controls the OCDS module, i.e.,specifies to the OCDS module when it has to carry out a particularaction(s), and evaluates information output by the OCDS module.

In the example considered, the above mentioned special features of theOCDS module lie in the OCDS module automatically deactivating thewatchdog timer if the OCDS module executes an action that alters thebehavior of the program-controlled unit.

The aforementioned action is an action:

-   -   that stops or interrupts the execution of the program that is to        be executed by the program-controlled unit; or    -   alters the speed with which the program to be executed by the        program-controlled unit is executed, that is to say, for        example, putting the program-controlled unit into the        single-step mode; or    -   that causes the program-controlled unit, more precisely, the        core C thereof, to execute instructions that are not part of the        (application) program that is to be actually executed by the        program-controlled unit, but, rather, are instructions serving        for the debugging or for the emulation of the program-controlled        unit.

The watchdog timer WD is deactivated by the OCDS module outputting adeactivation signal that is fed to the watchdog timer, more precisely, aterminal ONOFF provided for the activation and deactivation thereof,through a control line CTRL.

In the above mentioned situations, the watchdog timer WD is deactivatedautomatically, i.e., without the execution of a special instruction andwithout separate initiating by the external device controlling the OCDSmodule.

Normally, i.e., in program-controlled units without the OCDS moduleused-in the present case, the watchdog timer WD is activated anddeactivated exclusively through a non-illustrated system control unitconnected to the terminal ONOFF of the watchdog timer, the systemcontrol unit being caused to activate and deactivate the watchdog timerby instructions executed by the program-controlled unit or by a logicthat initializes the program-controlled unit after the resettingthereof. In other words, in program-controlled units without the OCDSmodule used in the present case, a special instruction would have to beexecuted to be able to reset the watchdog timer during the debugging oremulation of the program-controlled unit.

The automatic deactivation of the watchdog timer that is carried out bythe OCDS module used in the present case has a number of advantages oversuch processes. In particular, the invention makes the operation of theOCDS module simpler, and, furthermore, precludes a possible error sourceduring debugging or emulation. The reason for the first-mentionedadvantage is that it is no longer necessary to perform special actionsfor deactivating the watchdog timer. The reason for the second advantageis that the situation wherein the watchdog timer disturbs the debuggingor emulation of the program-controlled unit is reliably precluded; awatchdog timer that is inadvertently not deactivated could lead to theprogram-controlled unit being reset during the debugging or emulationthereof, the resetting itself and/or the cause thereof not being readilydiscernable.

The watchdog timer WD is activated again, preferably, after the end ofthe operations in response to which the watchdog timer was deactivated,that is to say, when the program-controlled unit executes theapplication program normally again (is not stopped, is not operating inthe single-step mode, is not executing instructions serving fordebugging or for emulation). What is achieved thereby is that theprogram-controlled unit—insofar as is possible under the givencircumstances—operates as in normal operation during the debugging oremulation thereof.

As a result of the above-described deactivation of the watchdog timerWD, the watchdog timer WD or at least specific parts thereof is or areturned off. In other words, a deactivated watchdog timer no longercounts or at least no longer initiates actions, if it reaches the countthat, when reached, would cause it to initiate, in the activated state,a resetting of the program-controlled unit or of parts thereof, or otheractions.

The deactivation of the watchdog timer WD can also be carried outdifferently than in the manner described above.

One of the possibilities suitable therefor lies in the OCDS modulecarrying out an automatic reconfiguration of the watchdog timer when theevents in response to which the watchdog timer is to be deactivatedoccur. Such reconfiguration may include, for example, in the count that,when reached, causes the watchdog timer to reset the program-controlledunit or parts thereof being set to a value that cannot be reached inphases in which the program-controlled unit behaves differently than innormal operation. By such or a different reconfiguration, it ispossible, as a result, to obtain the same effect as through theabove-described deactivation of the watchdog timer: the watchdog timerdoes not reset the program-controlled unit in phases in which the latterbehaves differently than in normal operation.

A further possibility for deactivating the watchdog timer lies in theOCDS module regularly resetting the watchdog timer in phases in whichthe program-controlled unit behaves differently than in normaloperation. What can be achieved by such a process, too, is that thewatchdog timer does not reset the program-controlled unit in phases inwhich the program-controlled unit behaves differently than in normaloperation.

The watchdog timer can, furthermore, be deactivated by the OCDS moduleensuring that the generation or the supply of the clock signal dependingon which the watchdog timer counts is prevented. As an alternative, itmight be provided that a clock signal with a lower frequency is fed tothe watchdog timer. What can be achieved by these measures, too, is thatthe watchdog timer does not reset the program-controlled unit in phasesin which the program-controlled unit behaves differently than in normaloperation.

For the sake of completeness, it is noted that the OCDS module alsoautomatically carries out the aforementioned alternatives to thefirst-described deactivation of the watchdog timer, if theprogram-controlled unit behaves differently than in normal operation.

Irrespective of all that, it may be provided that the OCDS moduleautomatically deactivates further or other components in addition to thewatchdog timer or instead of the watchdog timer, if theprogram-controlled unit behaves differently than in normal operation.One component for which this might prove to be advantageous is, by wayof example, but quite evidently not exclusively, a DMA controller.

The automatic deactivation of the watchdog timer or other components ofthe program-controlled unit may also be carried out by different debugresources than an OCDS module.

It may, furthermore, be provided that the OCDS module influences thewatchdog timer or other components of the program-controlled unitdifferently than by a deactivation. What influencing this may be dependson the respective individual case. It is an aim in each case to adaptthe behavior of the influenced components, by the influencing, asoptimally as possible to the altered behavior of the core. In such acase, optimum adaptation means that the influenced components, onaccount of the influencing, operate and cooperate such way precisely theerrors and disturbances that occur in normal operation of theprogram-controlled unit occur during the debugging or emulation of theprogram-controlled unit, in other words, if possible, the errors anddisturbances that occur are no more, no fewer, and no different than innormal operation of the program-controlled unit.

It may also be provided that the OCDS module or other debug resourcesautomatically influence the cooperation of specific components with oneanother and/or with the core, if the program-controlled unit behavesdifferently than in normal operation. For the sake of completeness, itis noted that this can be effected independently of the deactivationdescribed above.

A program-controlled unit in which such is the case is illustrated inFIG. 2.

The program-controlled unit shown in FIG. 2 contains:

-   -   a plurality of cores, more precisely, a first core C1, a second        core C2, and a third core C3;    -   a plurality of watchdog timers, more precisely, a first watchdog        timer WD1 assigned to the first core C1, a second watchdog timer        WD2 assigned to the second core C2, and a third watchdog timer        WD3 assigned to the third core C3;    -   an OCDS module including three components, more precisely, a        first OCDS module component OCDS1 assigned to the first core C1,        a second OCDS module component OCDS2 assigned to the second core        C2, and a third OCDS module component OCDS3 assigned to the        third core C3; and    -   for the remainder, corresponds to the program-controlled unit        shown in FIG. 1, i.e., contains diverse memory devices S1 to Sn        and peripheral units P1 to Pn.

The memory devices S1 to Sn may be common memory devices that can beaccessed by all the cores C1 to C3, or, alternatively, private memorydevices may be involved that can be accessed in each case only by aspecific core. The same applies correspondingly to the peripheral units.

For the remainder, the memory devices S1 to Sn and also the peripheralunits P1 to Pn correspond to the memory devices and peripheral units ofthe program-controlled unit in accordance with FIG. 1.

The cores C1 to C3 operate in parallel. They read data representinginstructions and operands from the memory devices S1 to Sn or from anexternal memory device that is provided outside the microcontroller andis not shown in FIG. 2, and execute the data.

The watchdog timers WD1 to WD3 in each case correspond to the watchdogtimer WD of the program-controlled unit in accordance with FIG. 1. Inother words, in each case counters are involved that:

-   -   automatically count upward or downward in a specific timing;    -   are reset when predetermined events occur; and    -   execute or initiate a specific action when a specific count is        reached, the action including, for example, in the watchdog        timer resetting, or putting into a specific other state, either        the program-controlled unit in its entirety or, alternatively,        at least one or more cores and/or one or more other components        of the program-controlled unit.

Although the watchdog timers WD1 to WD3 are respectively assigned to aspecific core, each of the watchdog timers can reset one or a pluralityof arbitrary cores when the specific count is reached. What watchdogtimer resets what core or what cores can be set in the watchdog timersor a non-illustrated control device.

The OCDS module components OCDS1 to OCDS3 in each case correspond to theOCDS module OCDS of the program-controlled unit in accordance withFIG. 1. However, they have a number of further special features bycomparison therewith.

In the example considered, these special features lie in the OCDS modulecomponents, when they execute an action that alters the behavior of oneof the cores, automatically altering the setting that defines whatwatchdog timer can reset what core.

The aforementioned actions are those actions in the case of which theOCDS module OCDS of the program-controlled unit in accordance with FIG.1 deactivates the watchdog timer WD.

As a result, to name just one of a virtually unlimited number ofexamples, a setting in the case of which each watchdog timer resets allthe cores in each case can be altered to the effect that each watchdogtimer resets only in each case those cores to which it is not assigned.

In such a case, the different OCDS module components OCDS1 to OCDS3 cancarry out different alterations of the settings. By way of example, itmay be provided:

-   -   that the first OCDS module component OCDS1, in the case where it        causes the core to which it is assigned, that is to say, the        core C1, to behave differently than in normal operation (e.g.,        to be stopped, to be operated in the single-step mode, or to        execute instructions serving for debugging or emulation), alters        the existing setting to the effect that the watchdog timer WD1        assigned to the core C1 resets none of the cores present, and        the other watchdog timers WD2 and WD3 can reset the core C2        and/or the core C3 but not the core C1;    -   that the second OCDS module component OCDS2, in the case where        it causes the core to which it is assigned, that is to say, the        core C2, to behave differently than in normal operation (e.g.,        to be stopped, to be operated in the single-step mode, or to        execute instructions serving for debugging or emulation), alters        the existing setting to the effect that the watchdog timer WD2        assigned to the core C2 resets none of the cores present, and        the other watchdog timers WD1 and WD3 can reset the core C1        and/or the core C3 but not the core C2; and    -   that the third OCDS module component OCDS3, in the case where it        causes the core to which it is assigned, that is to say, the        core C3, to behave differently than in normal operation (e.g.,        to be stopped, to be operated in the single-step mode, or to        execute instructions serving for debugging or emulation), alters        the existing setting to the effect that the watchdog timer WD3        assigned to the core C3 resets none of the cores present, and        the other watchdog timers WD1 and WD2 can reset the core C1        and/or the core C2 but not the core C3.

It goes without saying that any other combinations desired are alsopossible.

Furthermore, the OCDS module components can also influence whether and,if appropriate, what other components of the program-controlled unit arereset by the respective watchdog timers.

Preferably, the OCDS module components cause the setting alterations tobe entirely or partly reversed again if the core to which they arerespectively assigned is operating normally again (is no longer stopped,is no longer operating in the single-step mode, and is not executing aprogram serving for debugging or emulating, etc.).

As a result of the setting alterations that can be carried out by theOCDS module components, it is possible, during the debugging oremulation of the program-controlled unit, for the latter to be broughtinto a state in which the debugging or the emulation is disturbed aslittle as possible, and/or the program-controlled unit behaves as anormal operation—insofar as is possible under the givencircumstances—during the debugging or emulation.

Furthermore, it may (but need not) be provided that the OCDS modulecomponents can deactivate the watchdog timers like the OCDS module ofthe program-controlled unit in accordance with FIG. 1.

The program-controlled units described make it possible, independentlyof the details of the practical realization, for errors occurringtherein to be localized and eliminated under all circumstances rapidlyand simply.

1. A program-controlled unit, comprising: a plurality of cores forexecuting a program; a plurality of watchdog timers, each watchdog timerbeing configured to put one or more of the plurality of cores into aspecific state if a specific condition is reached; on-chip debugresources, located on the same chip as the program-controlled unit andsaid plurality of cores, said on-chip debug resources including aplurality of on-chip debug module components, each on-chip debug modulecomponent connected to one of said plurality of cores for tracking andinfluencing operations proceeding within said one of said plurality ofcores; said on-chip debug resources altering at least one setting thatdefines whether a particular one of said plurality of watchdog timerscan reset a particular one of said plurality of cores; other componentsconnected to at least one of said on-chip debug resources and at leastone of said plurality of cores; and said on-chip debug resourcesinfluencing at least one of: said other components; and cooperation ofsaid other components with at least one of: one another; and at leastone of said plurality of cores.
 2. The program-controlled unit accordingto claim 1, wherein said other components are components having behaviorinfluencing a behavior of at least one of said plurality of cores. 3.The program-controlled unit according to claim 1, wherein said othercomponents include at least one watchdog timer.
 4. Theprogram-controlled unit according to claim 1, wherein said on-chip debugresources perform at least one of: deactivate said other components;turn off said other components; place said other components into a givenstate; reset said other components; reconfigure said other components;and alter signals fed to said other components.
 5. Theprogram-controlled unit according to claim 1, wherein said on-chip debugresources deactivate said other components.
 6. The program-controlledunit according to claim 1, wherein said on-chip debug resources turn offsaid other components.
 7. The program-controlled unit according to claim1, wherein said on-chip debug resources place said other components intoa given state.
 8. The program-controlled unit according to claim 1,wherein said on-chip debug resources reset said other components.
 9. Theprogram-controlled unit according to claim 1, wherein said on-chip debugresources reconfigure said other components.
 10. The program-controlledunit according to claim 1, wherein said on-chip debug resources altersignals fed to said other components.
 11. The program-controlled unitaccording to claim 1, wherein the influencing of said other componentsby said on-chip debug resources is at least one of the group consistingof: a deactivation of said other components; a turning off of said othercomponents; a placement of said other components into a given state; areset of said other components; a reconfiguration of said othercomponents; and an alteration of signals fed to said other components.12. The program-controlled unit according to claim 1, wherein theinfluencing of said other components by said on-chip debug resources isa deactivation of said other components.
 13. The program-controlled unitaccording to claim 1, wherein the influencing of said other componentsby said on-chip debug resources is a turning off of said othercomponents.
 14. The program-controlled unit according to claim 1,wherein the influencing of said other components by said on-chip debugresources is a placement of said other components into a given state.15. The program-controlled unit according to claim 1, wherein theinfluencing of said other components by said on-chip debug resources isa reset of said other components.
 16. The program-controlled unitaccording to claim 1, wherein the influencing of said other componentsby said on-chip debug resources is a reconfiguration of said othercomponents.
 17. The program-controlled unit according to claim 1,wherein the influencing of said other components by said on-chip debugresources is an alteration of signals fed to said other components. 18.The program-controlled unit according to claim 1, wherein said on-chipdebug resources prevent said other components from cooperating.
 19. Theprogram-controlled unit according to claim 1, wherein the influencing ofcooperation of said other components is a prevention of cooperation. 20.The program-controlled unit according to claim 1, wherein said on-chipdebug resources initiate cooperation of components not otherwisecooperating.
 21. The program-controlled unit according to claim 1,wherein the influencing of cooperation of said other components is aninitiation of cooperation of components not otherwise cooperating. 22.The program-controlled unit according to claim 1, wherein, whenpredefined events occur, said on-chip debug resources automaticallycarry out at least one of: (a) influencing of said other components; and(b) the cooperation of said other components with at least one of, (i)one another and (ii) at least one of said plurality of cores.
 23. Theprogram-controlled unit according to claim 22, wherein said predefinedevents include an altering of an overall behavior by actions executed bysaid debug resources.
 24. The program-controlled unit according to claim22, wherein said predefined events include said on-chip debug resourcesexecuting actions altering a behavior of at least one of said pluralityof cores.
 25. The program-controlled unit according to claim 22, whereinsaid predefined events include said on-chip debug resources stoppingexecution of said program.
 26. The program-controlled unit according toclaim 22, wherein said predefined events include said on-chip debugresources altering a speed at which said program is executed.
 27. Theprogram-controlled unit according to claim 22, wherein said predefinedevents include said on-chip debug resources causing said core to executesaid program in a single-step mode.
 28. The program-controlled unitaccording to claim 22, wherein said predefined events include saidon-chip debug resources causing execution of instructions not part ofsaid program.
 29. The program-controlled unit according to claim 22,wherein said predefined events include said on-chip debug resourcescausing execution of instructions of one of a debugging program and anemulation program.
 30. A program-controlled unit, comprising: aplurality of cores for executing a program; a plurality of watchdogtimers, each watchdog timer being configured to put one or more of theplurality of cores into a specific state if a specific condition isreached; on-chip debug resources, located on the same chip as theprogram-controlled unit and said plurality of cores, connected to saidplurality of cores, for tracking and influencing operations proceedingwithin said plurality of cores; and said on-chip debug resources beingable to reconfigure said plurality of watchdog timers such that aspecific one of said cores can no longer be put into a specific state byany of the watchdog timers and at least one of the other cores stillbeing put into a specific state by at least one of the watchdog timers.31. A program-controlled unit, comprising: a plurality of cores forexecuting a program; a plurality of watchdog timers, each watchdog timerbeing configured to put one or more of the plurality of cores into aspecific state if a specific condition is reached; on-chip debugresources, located on the same chip as the program-controlled unit andsaid plurality of cores, connected to said plurality of cores, fortracking and influencing operations proceeding within said plurality ofcores; and said on-chip debug resources being able to alter a settingthat defines what watchdog timer can put what core into a specificstate.